As is known in the art, DRAM (Dynamic Random Access Memory) is significantly denser, e.g., more memory cells per unit area, than SRAM (Static Random Access Memory). Thus, using DRAM provides larger capacity per chip than SRAM implementations. DRAM is also significantly less expensive than SRAM at present. However, SRAM may be required when low latency access and/or deterministic access (no bank conflicts) are needed to meet system requirements. In real time applications having limited memory access time budgets, DRAM may not be an option due to successive accesses going to the same memory bank so as to increase the per reference access latency to unacceptable levels. Thus, designers typically prefer to use DRAM but select SRAM when DRAM does not meet one or more performance requirements, such as latency.
As is also known in the art, network processor units (NPUs) can use control structures to implement data queues and the like. Typical applications use DRAM to store data buffers of packets and SRAM for queue control data structures. SRAM is typically selected for queue control data structures due to potential DRAM bank conflicts and concomitant latency penalties since the queuing of packets or cells results in repeated references to queue descriptors and buffer descriptors stored in the same memory bank. U.S. Patent Application Publication No. 2003/0140196 A1, for example, describes an exemplary queue control implementation. The NPU holds the most recently used queue descriptors in an on chip cache. For enqueue and dequeue operations, when a queue descriptor is needed that is not contained in the cache, the least recently used (LRU) entry of the cache is evicted, and is replaced by fetching the needed queue descriptor from SRAM. However, the use of SRAM increases the overall cost and required real estate for the NPU.